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OCTOBER 2005
XRK4991
3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER
REV. 1.0.1
FUNCTIONAL DESCRIPTION
The XRK4991 is a 3.3V High-Speed Low-Voltage Programmable Skew Clock Buffer. It is intended for high-performance computer systems and offers user selectable control over system clock functions to optimize timing. Eight outputs, arranged in four banks, can each drive 50 terminated transmission lines while delivering minimal and specified output skews and full-swing Low Voltage TTL logic levels. Each bank (two outputs per bank) can be individually selected for one of nine delay or function configurations through two dedicated tri-level inputs. These outputs are able to lead or lag the CLKIN input reference clock by up to 6 time units from their nominal "zero" skew position. The integrated PLL allows external load and transmission line delay effects to be canceled achieving zero delay capability. Combining the zero delay capability with the selectable output skew functions, output-to-output delays of up to 12 time units can be created. The XRK4991's divide functions (divide-by-two and divide-by-four) allow distribution of a low-frequency clock that can be multiplied by two or four at the clock destination. This feature facilitates clock distribution while allowing maximum system clock flexibility.
FEATURES
* 3.75- to 85-MHz output operation * All output pair skew <100 ps typical * Three skew grades
-2 : tSKEW0<250ps -5 : tSKEW0<500ps -7 : tSKEW0<700ps
* Selectable output functions
Skew adjustments of +/- 6tU (up to 18 ns) Inverted and non-inverted Operation at 1/2 and 1/4 input frequency Operation at 2x and 4x input frequency
* Cycle-Cycle Jitter
< 25 ps (rms) < 200 ps (pk-pk)
* Zero input-to-output delay * 50% duty-cycle outputs * LVTTL outputs drive 50 terminated lines * Operates from a single 3.3V supply * 32-pin PLCC package * Green packaging * Lead free lead frame available
FIGURE 1. BLOCK DIAGRAM OF THE XRK4991
H M CLKIN Ref L
QA0 QA1
PLL
FB_IN Feedback
QB0 QB1
FSEL* PLL_BYPASS*
Bank "SKEW" Control
QC0 QC1
SELA[1:0]* SELB[1:0]* SELC[1:0]* SELD[1:0]* * Tri-Level inputs
2 2 2 2
QD0 QD1
Exar Corporation 48720 Kato Road, Fremont CA, 94538 * (510) 668-7000 * FAX (510) 668-7017 * www.exar.com
XRK4991 3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER
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PRODUCT ORDERING INFORMATION
PRODUCT NUMBER XRK4991IJ-2 XRK4991CJ-2 XRK4991IJ-5 XRK4991CJ-5 XRK4991CJ-7 ACCURACY 250 ps 250 ps 500 ps 500 ps 750 ps TEMPERATURE RANGE -40C to +85C 0C to +70C -40C to +85C 0C to +70C 0C to +70C
FIGURE 2. PIN OUT OF THE XRK4991
PLL_BYPASS 31
SELC0
4 SELC1 SELD0 SELD1 VCCQ VCCN QD1 QDO GND GND 5 6 7 8 9 10 11 12 13 14 QC1
3
2
1
32
30 29 28 27 26 SELB0 GND SELA1 SELA0 VCCN QA0 QA1 GND GND
XRK4991
SELB1 25 24 23 22 21 20 QB0
CLKIN 17 FB_IN
FSEL
15 QC0
16 VCCN
18 VCCN
GND
VCCQ
19 QB1
2
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XRK4991 3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER
PIN DESCRIPTIONS
PIN NAME CLKIN FB_IN FSEL PLL_BYPASS SELA0 SELA1 SELB0 SELB1 SELC0 SELC1 SELD0 SELD1 QA0 QA1 QB0 QB1 QC0 QC1 QD0 QD1 VCCN PIN # 1 17 3 31 26 27 29 30 4 5 6 7 24 23 20 19 15 14 11 10 9 16 18 25 2 8 12 13 21 22 28 32 TYPE I I I I I Reference clock input. PLL's feedback input. (Normally connected to one of the eight outputs) Tri-level frequency range select. See Table 1 Tri-level select. See PLL_BYPASS section. Tri-level select inputs for Bank A outputs (QA0, QA1). See Table 2. DESCRIPTION
I
Tri-level select inputs for Bank B outputs (QB0, QB1). See Table 2.
I
Tri-level select inputs for Bank C outputs (QC0, QC1). See Table 2.
I
Tri-level select inputs for Bank D outputs (QD0, QD1). See Table 2.
O
Bank A output pair. See Table 2.
O
Bank B output pair. See Table 2.
O
Bank C output pair. See Table 2.
O
Bank D output pair. See Table 2.
PWR
Power supply for output drivers.
VCCQ GND
PWR
Power supply for internal circuitry.
PWR
Ground.
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XRK4991 3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER TABLE 1: FREQUENCY RANGE SELECT AND tU CALCULATION [1] fNOM (MHZ)
FSEL[2] LOW MID HIGH[3] MIN 15 25 40 MAX 30 50 85
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tU = 1 / (fNOM X N)
WHERE
APPROXIMATE FREQUENCY (MHZ) AT
WHICH tU
N=
= 1.0ns
44 26 16
22.7 38.5 62.5
SKEW SELECT CONTROL
The skew select control consists of four independent banks. Each bank has two low-skew, high-fanout drivers (Qx0, Qx1), and two corresponding tri-level function select (SELx0, SELx1) inputs. The nine possible output states for each bank are shown in Table 2 as determined by each bank's select inputs. All timing measurements are made with respect to the CLKIN input with the output connected to the FB_IN input configured for 0 tU operation. TABLE 2: PROGRAMMABLE SKEW CONFIGURATIONS [1]
FUNCTION SELECT INPUTS SELX1 LOW LOW LOW MID MID MID HIGH HIGH HIGH SELX0 LOW MID HIGH LOW MID HIGH LOW MID HIGH QA[1:0], QB[1:0] -4tU -3tU -2tU -1tU 0tU +1tU +2tU +3tU +4tU OUTPUT FUNCTIONS QC[1:0] /2 -6tU -4tU -2tU 0tU +2tU +4tU +6tU /4 QD[1:0] /2 -6tU -4tU -2tU 0tU +2tU +4tU +6tU Inverted
NOTES: 1. For all tri-level (three-state) inputs, HIGH indicates a connection to VCC, LOW indicates a connection to GND, and MID indicates an open connection. Internal termination circuitry holds an unconnected input to VCC/2. 2. The level to be set on FSEL is determined by the "normal" operating frequency (fNOM) of the PLL. Nominal frequency (fNOM) always appears at QA0 and the other outputs when they are operated in their undivided modes (see Table 2). The frequency appearing at the CLKIN and FB_IN inputs will be fNOM when the output connected to FB_IN is undivided. The frequency of the CLKIN and FB_IN inputs will be fNOM / 2 or fNOM / 4 when the part is configured for a frequency multiplication. 3. When the FSEL pin is selected HIGH, the CLKIN input must not transition upon power-up until VCC has reached 2.8V.
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XRK4991 3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER
FIGURE 3. TYPICAL OUTPUTS WITH FB_IN CONNECTED TO A ZERO-SKEW OUTPUT t0+1tU t0+2tU t0+3tU t0+4tU t0+5tU t0+6tU
t0-6tU
t0-5tU
t0-4tU
t0-3tU
t0-2tU
t0-1tU
FB_IN SELA[1:0] SELB[1:0] (N/A) LL LM LH ML MM MH HL HM HH (N/A) (N/A) (N/A) CLKIN SELC[1:0] SELD[1:0] -6tU LM -4tU LH -3tU (N/A) -2tU ML -1tU (N/A) 0tU MM +1tU (N/A) +2tU MH +3tU (N/A) +4tU HL +6tU HM LL/HH DIVIDED HH(D) INVERT
PLL_BYPASS
The PLL_BYPASS input is a tri-level input. In normal system operation, this pin is connected to ground. In normal operation (tied LOW) all outputs will function based only on the connection of their own function select inputs (SELx[1:0]) and the waveform characteristics of the PLL. If the PLL_BYPASS input is forced to its MID or HIGH state the device will operate in PLL bypass mode, with the phase locked loop disconnected, and CLKIN waveforms will directly control all outputs. Relative output to output timing is controlled by the SELx[1:0], the same as in normal mode.
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XRK4991 3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER
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ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Storage Temperature Ambient Temperature with Power Applied Supply Voltage to Ground Potential DC Input Voltage Output Current into Outputs (LOW) Static Discharge Voltage (per MIL-STD-883, Method 3015) Latch-Up Current. -65C to +150C -55C to +125C -0.5V to +7.0V -0.5V to +7.0V 64 mA >3000V >200 mA
OPERATING RANGE
RANGE Industrial Commercial AMBIENT TEMPERATURE -40C to +85C 0C to +70C VCC 3.3 + 10% 3.3 + 10%
ELECTRICAL CHARACTERISTICS OVER THE 3.3V + 10% OPERATING RANGE
SYMBOL VOH VOL VIH VIL VIHH DESCRIPTION Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage tri-level Input HIGH Voltage (FSEL, SELx[1:0], Test) [4] VIMM tri-level Input MID Voltage (FSEL, SELx[1:0], Test) VILL
[4]
MIN 2.4
MAX
UNIT V
CONDITION VCC = Min., IOH = -18mA VCC = Min., IOL = 35mA (CLKIN and FB_IN inputs only) Min. < VCC < Max.
0.45 2.0 -0.5 0.87*VCC VCC 0.8 VCC
V V V V
0.47*VCC
0.53 * VCC
V
Min. < VCC < Max.
tri-level Input LOW Voltage (FSEL, SELx[1:0], Test)
[4]
0.0
0.13 * VCC
V
Min. < VCC < Max.
IIH IIL IIHH IIMM IILL
Input HIGH Leakage Current (CLKIN and FB_IN inputs only) Input LOW Leakage Current (CLKIN and FB_IN inputs only) Input HIGH Current (FSEL, SELx[1:0], Test) Input MID Current (FSEL, SELx[1:0], Test) Input LOW Current (FSEL, SELx[1:0], Test) -50 -20
20

VCC = Max., VIN = Max. VCC = Max., VIN = 0.4V VIN = VCC VIN = VCC/2 VIN = GND
200
A A
50
-200
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XRK4991 3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER
ELECTRICAL CHARACTERISTICS OVER THE 3.3V + 10% OPERATING RANGE
SYMBOL IOS DESCRIPTION Short Circuit Current [5] MIN MAX -200 UNIT mA CONDITION VCC = Max, VOUT = GND (25 only) ICCQ Operating Current Used by Internal Circuitry Com'l Ind 95 100 19 mA mA VCCN = VCCQ = Max., All Inputs Selects Open VCCN = VCCQ = Max., IOUT = 0 mA Inputs Selects Open, fMAX PD Power Dissipation per Output Pair [7] 104 mW VCCN = VCCQ = Max., IOUT = 0 mA Input Selects Open, fMAX
ICCN
Output Buffer Current per Output Pair [6]
CAPACITANCE[8]
SYMBOL CIN Input Capacitance DESCRIPTION MAX. 10 UNIT pF CONDITION TA = 25C, f=1MHz, VCC=3.3V
NOTES: 4. These inputs are normally wired to VCC, GND or left unconnected (actual threshold voltages vary as a percentage of VCC). Internal termination resistors hold unconnected inputs at VCC/2. If these inputs are switched, the function and timing of the outputs may glitch and the PLL may require an additional tLOCK time before all data sheet limits are achieved. 5. XRK4991 should be tested one output at a time, output shorted for less than one second, less than 10% duty cycle. Room temperature only. 6. Total output current per output pair can be approximated by the following expression that includes device current plus load current: XRK4991: ICCN = {(4+0.11F) + [(835-3F)/Z + (.0022FC)]N} x 1.1 Where: F = frequency in MHz C = capacitive load in pF Z = line impedance in ohms N = number of loaded outputs; 0, 1, or 2 7. Total power dissipation per output pair can be approximated by the following expression that includes device power dissipation plus power dissipation due to the load circuit: PD = {(22 + 0.61F) + [(1550 + 2.7F)/Z) + .0125FC]N} x 1.1 See note 6 for variable definition. 8. Applies to CLKIN and FB_IN inputs only.
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XRK4991 3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER FIGURE 4. AC TEST LOAD
VCC R1 CL R2 LOAD R1 = 100 R2 = 100 CL = 30pF (Includes fixture and probe capacitances )
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FIGURE 5. INPUT TEST WAVEFORM 3.0V 2.0V Vth = 1.5V 0.8V 0.0V <1ns <1ns 2.0V Vth = 1.5V 0.8V
SWITCHING CHARACTERISTICS OVER THE OPERATING RANGE [2,9]
SYMBOL fNOM DESCRIPTION Operating Clock Frequency in MHz FSEL = LOW [1, 2] FSEL = MID [1, 2] FSEL = HIGH [1, 2, 3] MIN 15 25 40 MAX 30 50 85 UNIT MHz
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XRK4991 3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER
SWITCHING CHARACTERISTICS OVER THE 3.3V + 10% OPERATING RANGE [2,9]
XRK4991-2 SYMBOL tRPWH tRPWL tu tSKEWPR tSKEW0 tSKEW1 tSKEW2 tSKEW3 tSKEW4 tDEV tPD tODCV tPWH tPWL tORISE tOFALL tLOCK tJR DESCRIPTION MIN CLKIN Pulse Width HIGH CLKIN Pulse Width LOW Programmable Skew Unit Zero Output Matched-Pair Skew (Qx[1:0]) [10, 11] Zero Output Skew (All Outputs) [10, 12] Output Skew (Rise-Rise, Fall-Fall, Same Class Outputs) [10, 13] Output Skew (Rise-Fall, NominalInverted, Divided-Divided) [10, 13] Output Skew (Rise-Rise, Fall-Fall, Different Class Outputs) [10, 13] Output Skew (Rise-Fall, NominalDivided, Divided-Inverted [10, 13] Device-to-Device Skew [14, 15] Propagation Delay, CLKIN Rise to FB_IN Rise Output Duty Cycle Variation [16] Output HIGH Time Deviation from 50%
[17]
XRK4991-5 MIN 4 4 See Table 1 TYP MAX
XRK4991-7 UNIT MIN 4 4 TYP MAX ns ns
TYP
MAX
4 4
0.05
0.2
0.1
0.25
0.1
0.25
ns
0.1 0.25
0.25 0.5
0.25 0.6
0.5 0.7
0.3 0.6
0.75 1
ns ns
0.3
1
0.5
1
1
1.5
ns
0.25
0.5
0.5
0.7
0.7
1.2
ns
0.5
0.9
0.5
1
1.2
1.7
ns
0.75 -0.25 -0.65 0 0 0.25 0.65 2.0 1.5 0.15 0.15 1 1 1.2 1.2 0.5 0.15 0.15 1 1 -0.5 -1 0 0
1.25 0.5 1 2.5 3 1.5 1.5 0.5 25 200 0.15 0.15 1.5 1.5 -0.7 -1.2 0 0
1.65 0.7 1.2 3 3.5 2.5 2.5 0.5 25 200
ns ns ns ns ns ns ns ms ps
Output LOW Time Deviation from 50%
[17]
Output Rise Time [17, 18] Output Fall Time [17, 18] PLL Lock Time [19] Cycle-to-Cycle Output Jitter RMS [14] Peak-to-Peak
[14]
25 200
NOTES: 9. Test measurement levels for the XRK4991 are TTL levels (1.5V to 1.5V). Test conditions assume signal transition times of 2 ns or less and output loading as shown in the AC Test Loads and Waveforms unless otherwise specified. 10. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with 30pF and terminated with 50 to VCC/2 (XRK4991).
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XRK4991 3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER
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11. tSKEWPR is defined as the skew between a pair of outputs (Qx0 and Qx1) when all eight outputs are selected for 0tU. 12. tSKEW0 is defined as the skew between outputs when they are selected for 0tU. Other outputs are divided or inverted but not shifted 13. There are three classes of outputs: Nominal (multiple of tU delay), Inverted (QD[1:0] only with SELD0 = SELD1 = HIGH), and Divided (QC[1:0] and QD[1:0] only in Divide-by-2 or Divide-by-4 mode). 14. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters. 15. tDEV is the output-to-output skew between any two devices operating under the same conditions (VCC ambient temperature, air flow, etc.) 16. tODCV is the deviation of the output from a 50% duty cycle. Output pulse width variations are included in tSKEW2 and tSKEW4 specifications. 17. Specified with outputs loaded with 30pF for the XRK4991-5 and -7 devices. Devices are terminated through 50 to VCC/2. tPWH is measured at 2.0V. tPWL is measured at 0.8V. 18. tORISE and tOFALL measured between 0.8V and 2.0V. 19. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This parameter is measured from the application of a new signal or frequency at CLKIN or FB_IN until tPD is within specified limits
FIGURE 6. AC TIMING DIAGRAMS
tREF tRPWH CLKIN tPD FB_IN tJR Qxx output tODCV tODCV tRPWL
tSKEWPR, tSKEW0, 1
Other Qxx output
tSKEWPR, tSKEW0, 1
tSKEW2
Inverted Qxx output
tSKEW2
tSKEW3, 4
CLKIN Divided by 2
tSKEW3, 4
tSKEW3, 4
tSKEW1, 3, 4
CLKIN Divided by 4
tSKEW2, 4
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XRK4991 3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER
PACKAGE DIMENSIONS
32 LEAD PLASTIC LEADED CHIP CARRIER (PLCC)
Rev. 1.00
D A1 D1 30 x H1
2 1 32
A2 45 x H2
B1
Corner Chamfer
E3
E1
E
B
D2
e 72 deg typ.
C D3 A
INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX A 0.120 0.140 3.05 3.56 A1 0.075 0.095 1.91 2.41 A2 0.020 --0.51 --B 0.013 0.021 0.33 0.53 B1 0.026 0.032 0.66 0.81 C 0.008 0.013 0.19 0.32 D 0.485 0.495 12.33 12.58 D1 0.448 0.454 11.39 11.54 D2 0.400 0.440 10.17 11.18 0.300 typ. 7.62 typ. D3 E 0.585 0.595 14.87 15.11 E1 0.545 0.557 13.85 14.15 E2 0.500 0.540 12.71 13.72 0.400 typ. 10.16 typ. E3 0.050 BSC 1.27 BSC e H1 0.023 0.029 0.58 0.74 H2 0.042 0.048 1.07 1.22 R 0.025 0.045 0.64 1.14 Note: The control dimension is in inches.
R SEATING PLANE
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XRK4991 3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER
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REVISION HISTORY
REVISION # 1.0.0 1.0.1 DATE June 17, 2005 Initial Release to Production DESCRIPTION
October 5, 2005 Product ordering information: Remove "F" product numbers and Lead Free column.
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2005 EXAR Corporation Datasheet October 2005. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
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